1. Field of the Invention
The present invention relates to a fault-tolerant computer with duplex systems and a method of controlling such a fault-tolerant computer.
2. Description of the Related Art
In recent years, growing computer functionality has enabled computers to be used in a wider variety of fields. Such computers are required to operate continuously even in the event of faults. One solution to meet the requirement is fault-tolerant technology as disclosed in Japanese laid-open patent publication No. 1998-177498, for example.
A fault-tolerant computer built on the fault-tolerant technology has duplex systems each including a CPU subsystem and an IO subsystem. The fault-tolerant computer detects the occurrence of a fault by comparing the duplex systems to ascertain whether the systems are operating in synchronism with each other or not.
Fault-tolerant computers with duplex systems employs a lock-step system for operating the two CPU subsystems synchronously with each other based on a common internal clock. Some fault-tolerant computers have a high-speed interface for communications between the two IO subsystems, the interface employing a serial link that operates out of synchronism with the internal clock. When one of the IO subsystems accesses the two CPU subsystems of those fault-tolerant computers, one of the CPU subsystems is accessed only through an internal path, whereas the other CPU subsystem is accessed through the high-speed interface. In order to gain synchronous access to the two CPU subsystems, therefore, the internal clock and the clock of the high-speed interface need to be synchronized with each other.
It has been customary to achieve synchronized communication timing between the CPU subsystems and the IO subsystems of the duplex systems by replacing the clock of the high-speed interface with the internal clock at a given time within certain cyclic periods.
However, the fault-tolerant computers have suffered a problem in that though the two systems operate based on the same clock, they tend to be shifted out of phase with each other due to a skew on clock lines and characteristics of PLLs in the systems. The problem has led to another disadvantage in that there are statically indefinite parameters exist in the receiving system.
Since the internal clock for operating the systems and the clock of the high-speed interface are different from each other, synchronism is achieved using a gearing generated from a global counter. However, unless the global counter and other component are stable, no gearing can be generated, and the receiving system has to perform data communications out of synchronism until a gearing is generated.